Fast Bit Compressor: A Novel Implementation of a Low Latency Modulation Using Binary Signals on Bandwidth Limited Links
نویسندگان
چکیده
Pulse-width modulation (PWM) is known for simple digital-to-analog conversion and motor current control. But up to now, PWM is not known for high speed communication. This paper shows how to implement the physical layer of a fully digital PWM-based communication system. For performance reasons the PWM senders and receivers are implemented using asynchronous logic. The proposed calibration procedure enables an adaption to a given channel bandwidth. A proof-of-concept is implemented on low-cost Cyclone II FPGAs. The experimental results regarding a single 1 m coaxial cable, are promising. An FPGA clock frequency of only 333 MHz is sufficient to achieve a data rate of 1 GBit/s, which is faster than every other communication means of this specific FPGA.
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